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cy7c1370b cy7c1372b 512k 36/1m 18 pipelined sram with nobl ? architecture cypress semiconductor corporation 3901 north first street san jose, ca 95134 408-943-2600 document #: 38-05197 rev. *c revised january 18, 2003 features ? zero bus latency, no dead cycles between write and read cycles fast clock speed: 200, 167, 150, and 133 mhz fast access time: 3.0, 3.4, 3.8, and 4.2 ns internally synchronized registered outputs eliminate the need to control oe single 3.3v ?5% and +10% power supply v dd separate v ddq for 3.3v or 2.5v i/o single we (read/write) control pin positive clock-edge triggered address, data, and control signal registers for fully pipelined applications interleaved or linear four-word burst capability individual byte write (bws a?bws d) control (may be tied low) cen pin to enable clock and suspend operations three chip enables for simple depth expansion jtag boundary scan (bga package only) available in 119-ball bump bga and 100-pin tqfp packages automatic power down available using zz mode or ce deselect functional description the cy7c1370b and cy7c1372b srams are designed to eliminate dead cycles when transitions from read to write or vice versa. these srams are optimized for 100 percent bus utilization and achieve zero bus latency ? . they integrate 524,288 36 and 1,048,576 18 sram cells, respectively, with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. the synchronous burst sram family employs high-speed, low-power cmos designs using advanced single-layer polysilicon, three-layer metal technology. each memory cell consists of six transistors. all synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (clk). the synchronous inputs include all addresses, all data inputs, depth-expansion chip enables (ce 1 , ce 2 , and ce 3 ), cycle start input (adv/ld ), clock enable (cen ), byte write enables (bws a, bws b, bws c, and bws d), and read-write control (we ). bws c and bws d apply to cy7c1370b only. address and control signals are applied to the sram during one clock cycle, and two cycles later, its associated data occurs, either read or write. a clock enable (cen ) pin allows operation of the cy7c1370b/cy7c1372b to be suspended as long as necessary. all synchronous inputs are ignored when cen is high and the internal device registers will hold their previous values. there are three chip enable pins (ce 1 , ce 2 , ce 3 ) that allow the user to deselect the device when desired. if any one of these three are not active when adv/ld is low, no new memory operation can be initiated and any burst cycle in progress is stopped. however, any pending data transfers (read or write) will be completed. the data bus will be in high-impedance state two cycles after the chip is deselected or a write cycle is initiated. the cy7c1370b and cy7c1372b have an on-chip two-bit burst counter. in the burst mode, the cy7c1370b and cy7c1372b provide four cycles of data for a single address presented to the sram. the order of the burst sequence is defined by the mode input pin. the mode pin selects between linear and interleaved burst sequence. the adv/ld signal is used to load a new external address (adv/ld = low) or increment the internal burst counter (adv/ld = high) output enable (oe ) and burst sequence select (mode) are the asynchronous signals. oe can be used to disable the outputs at any given time. zz may be tied to low if it is not used. four pins are used to implement jtag test capabilities. the jtag circuitry is used to serially shift data to and from the device. jtag inputs use lvttl/lvcmos levels to shift data during this testing mode of operation. clk ax cen we bws x ce 1 ce ce 2 oe 256k 36/ memory array logic block diagram dq x data-in reg. q d ce control and write logic 3 adv/ld mode dp x cy7c1370 cy7c1372 a x dq x dp x bws x 512k 18 x = 18:0 x = 19:0 x = a, b, c, d x = a, b x = a, b x = a, b x = a, b, c, d x = a, b, c, d outout registers and logic
cy7c1370b cy7c1372b document #: 38-05197 rev. *c page 2 of 27 . selection guide 200 mhz 167 mhz 150 mhz 133 mhz unit maximum access time 3.0 3.4 3.8 4.2 ns maximum operating current commercial 315 285 265 245 ma maximum cmos standby current 20 20 20 20 ma pin configurations a a a a a1 a0 dnu dnu v ss v dd a a a a a a v ddq v ss dqb dqb dqb v ss v ddq dqb dqb v ss nc v dd dqa dqa v ddq v ss dqa dqa v ss v ddq v ddq v ss dqc dqc v ss v ddq dqc dqc v dd v ss dqd dqd v ddq v ss dqd dqd dqd v ss v ddq a a ce 1 ce 2 bws a ce 3 v dd v ss clk we cen oe a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a adv/ld zz dnu cy7c1370b 100-pin tqfp packages a a a a a1 a0 dnu dnu v ss v dd a a a a a a a nc nc v ddq v ss nc dpa dqa dqa v ss v ddq dqa dqa v ss nc v dd dqa dqa v ddq v ss dqa dqa nc nc v ss v ddq nc nc nc nc nc nc v ddq v ss nc nc dqb dqb v ss v ddq dqb dqb nc v dd v ss dqb dqb v ddq v ss dqb dqb dpb nc v ss v ddq nc nc nc a a ce 1 ce 2 nc nc bws b bws a ce 3 v dd v ss clk we cen oe a a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a adv/ld zz mode dnu bws d mode bws c dqc dqc dqc dqc dpc dqd dqd dpd dqd nc dpb dqb dqa dqa dqa dqa dpa dqb dqb (512k 36) bws b nc nc a dnu dnu 50 cy7c1372b (1m 18)
cy7c1370b cy7c1372b document #: 38-05197 rev. *c page 3 of 27 pin configurations (continued) 234567 1 a b c d e f g h j k l m n p r t u dqa v ddq nc nc dqc dqd dqc dqd aa aa av ddq ce 2 a v ddq v ddq v ddq v ddq nc nc a dqc dqc dqd dqd tms v dd a 64m dpd a a adv/ld ace 3 nc v dd aanc v ss v ss nc dpb dqb dqb dqa dqb dq b dqa dqa nc tdi tdo v ddq tck v ss v ss v ss nc v ss v ss v ss v ss mode ce 1 v ss oe v ss v ddq bws ca v ss we v ddq v dd nc v dd v ss clk nc bws a cen v ss v ddq v ss zz nc a a a1 a0 v ss v dd nc cy7c1370b (512k 36) ? 7 17 bga dpc dqb a32m dqc dqb dqc dqc dqc dqb dqb dqa dqa dqa dqa dpa dqd dqd dqd dqd bws d 119-ball bump bga bws b 234567 1 a b c d e f g h j k l m n p r t u 32m dqa v ddq nc nc nc dqb dqb dqb dqb aa aa av ddq ce 2 a nc v ddq nc v ddq v ddq v ddq nc nc nc 64m a dqb dqb dqb dqb nc nc nc nc tms v dd a a dpb a a adv/ld ace 3 nc v dd aanc v ss v ss nc nc dpa dqa dqa dqa dqa dqa dqa dqa nc tdi tdo v ddq tck v ss v ss v ss nc v ss v ss v ss v ss v ss mode ce 1 v ss nc oe v ss v ddq bws ba v ss nc v ss we nc v ddq v dd nc v dd nc v ss clk nc nc bws a cen v ss nc v ddq v ss nc zz nc a a a a1 a0 v ss nc v dd nc cy7c1372b (1m 18) ? 7 17 bga
cy7c1370b cy7c1372b document #: 38-05197 rev. *c page 4 of 27 pin configurations (continued) cy7c1370b (512k 36) ? 11 15 fbga 165-ball bump fbga cy7c1372b (1m 18) ? 11 15 fbga 234567 1 a b c d e f g h j k l m n p r tdo nc nc nc nc dpb nc dqb ace 1 nc ce 3 bws bcen ace 2 nc dqb dqb mode nc dqb dqb nc nc nc 32m 64m v ddq nc bws a clk we v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss nc v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck a0 v ss atdi atms dqb v ss nc v ss dqb nc v dd v ss v ss v ss v ss nc v ss a1 dqb nc nc nc v ddq v ss 891011 nc aa adv/ld a oe a a 128m v ss v ddq nc dpa v ddq v dd nc dqa dqa nc nc nc dqa nc v dd v ddq v dd v ddq dqa v dd nc v dd nc v dd v ddq dqa v ddq v dd v dd v ddq v dd v ddq nc v ddq a a v ss aa aa dqa nc nc zz dqa nc nc dqa a v ddq 234567 1 a b c d e f g h j k l m n p r tdo nc nc dpc dqc dpd nc dqd ace 1 bws bce 3 bws ccen ace 2 dqc dqd dqd mode nc dqc dqc dqd dqd dqd 32m 64m v ddq bws dbws a clk we v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss nc v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck a0 v ss atdi atms dqc v ss dqc v ss dqc dqc v dd v ss v ss v ss v ss nc v ss a1 dqd dqd nc nc v ddq v ss 891011 nc aa adv/ld nc oe a a 128m v ss v ddq nc dpb v ddq v dd dqb dqb dqb nc dqb nc dqa dqa v dd v ddq v dd v ddq dqb v dd nc v dd dqa v dd v ddq dqa v ddq v dd v dd v ddq v dd v ddq dqa v ddq a a v ss aa aa dqb dqb dqb zz dqa dqa dpa dqa a v ddq
cy7c1370b cy7c1372b document #: 38-05197 rev. *c page 5 of 27 pin definitions name i/o type description a0 a1 a input- synchronous address inputs used to select one of the 524,288/1,048576 address locations . sampled at the rising edge of the clk. bws a bws b bws c bws d input- synchronous byte write select inputs, active low . qualified with we to conduct writes to the sram. sampled on the rising edge of clk. bws a controls dqa and dpa, bws b controls dqb and dpb, bws c controls dqc and dpc, bws d controls dqd and dpd. we input- synchronous write enable input, active low . sampled on the rising edge of clk if cen is active low. this signal must be asserted low to initiate a write sequence. adv/ld input- synchronous advance/load input used to advance the on-chip address counter or load a new address . when high (and cen is asserted low) the internal burst counter is advanced. when low, a new address can be loaded into the device for an access. after being deselected, adv/ld should be driven low in order to load a new address. clk input-clock clock input . used to capture all synchronous inputs to the device. clk is qualified with cen . clk is only recognized if cen is active low. ce 1 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select/deselect the device. ce 2 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select/deselect the device. ce 3 input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select/deselect the device. oe input- asynchronous output enable, active low . combined with the synchronous logic block inside the device to control the direction of the i/o pins. when low, the i/o pins are allowed to behave as outputs. when deasserted high, i/o pins are three-stated, and act as input data pins. oe is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state and when the device has been deselected. cen input- synchronous clock enable input, active low . when asserted low the clock signal is recognized by the sram. when deasserted high the clock signal is masked. since deasserting cen does not deselect the device, cen can be used to extend the previous cycle when required. dqa dqb dqc dqd i/o- synchronous bidirectional data i/o lines . as inputs, they feed into an on-chip data register that is triggered by the rising edge of clk. as outputs, they deliver the data contained in the memory location specified by a x during the previous clock rise of the read cycle. the direction of the pins is controlled by oe and the internal control logic. when oe is asserted low, the pins can behave as outputs. when high, dqa ? dqd are placed in a three-state condition. the outputs are automatically three-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of oe .dq a, b, c and d are eight-bits wide. dpa dpb dpc dpd i/o- synchronous bidirectional data parity i/o lines . functionally, these signals are identical to dq[31:0]. during write sequences, dpa is controlled by bws a, dpb is controlled by bws b, dpc is controlled by bws c, and dpd is controlled by bws d.dp a, b, c and d are one-bit wide zz input- asynchronous zz ? sleep ? input . this active high input places the device in a non-time critical ? sleep ? condition with data integrity preserved. mode input pin mode input . selects the burst order of the device. tied high selects the interleaved burst order. pulled low selects the linear burst order. mode should not change states during operation. when left floating mode will default high, to an interleaved burst order. v dd power supply power supply inputs to the core of the device . v ddq i/o power supply power supply for the i/o circuitry . tdo jtag serial output synchronous serial data-out to the jtag circuit . delivers data on the negative edge of tck (bga only).
cy7c1370b cy7c1372b document #: 38-05197 rev. *c page 6 of 27 tdi jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck.(bga only) tms te s t m o d e s e l e c t synchronous this pin controls the test access port (tap) state machine . sampled on the rising edge of tck (bga only). tck jtag serial clock serial clock to the jtag circuit (bga only). 32m 64m 128m ? no connects . reserved for address expansion. pins are not internally connected. v ss ground ground for the device . should be connected to ground of the system. nc ? no connects . pins are not internally connected. dnu ? do not use pins . pin definitions name i/o type description
cy7c1370b cy7c1372b document #: 38-05197 rev. *c page 7 of 27 introduction functional overview the cy7c1370b/cy7c1372b are synchronous-pipelined burst nobl ? srams designed specifically to eliminate wait states during write/read transitions. all synchronous inputs pass through input registers controlled by the rising edge of the clock. the clock signal is qualified with the cen input signal. if cen is high, the clock signal is not recognized and all internal states are maintained. all synchronous operations are qualified with cen . all data outputs pass through output registers controlled by the rising edge of the clock. maximum access delay from the clock rise (t co ) is 3.8 ns (150-mhz device). accesses can be initiated by asserting all three chip enables (ce 1 , ce 2 , ce 3 ) active at the rising edge of the clock. if the cen is active low and adv/ld is asserted low, the address presented to the device will be latched. the access can either be a read or write operation, depending on the status of the write enable (we ). bws [d:a] can be used to conduct byte write operations. write operations are qualified by the write enable (we ). all writes are simplified with on-chip synchronous self-timed write circuitry. three synchronous ce 1 , ce 2 , ce 3 and an asynchronous oe simplify depth expansion. all operations (reads, writes, and deselects) are pipelined. adv/ld should be driven low once the device has been deselected in order to load a new address for the next operation. single read accesses a read access is initiated when the following conditions are satisfied at clock rise: (1) cen is asserted low, (2) ce 1 , ce 2 , and ce 3 are all asserted active, (3) the write enable input signal we is deasserted high, and (4) adv/ld is asserted low. the address presented to the address inputs is latched into the address register and presented to the memory core and control logic. the control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. at the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus within 3.8 ns (150-mhz device) provided oe is active low. after the first clock of the read access the output buffers are controlled by oe and the internal control logic. oe must be driven low in order for the device to drive out the requested data. during the second clock, a subsequent operation (read/write/deselect) can be initiated. deselecting the device is also pipelined. therefore, when the sram is deselected at clock rise by one of the chip enable signals, its output will three-state following the next clock rise. burst read accesses the cy7c1370b/cy7c1372b have on-chip burst counters that allow the user the ability to supply a single address and conduct up to four reads without reasserting the address inputs. adv/ld must be driven low in order to load a new address into the sram, as described in the single read access section above. the sequence of the burst counter is determined by the mode input signal. a low input on mode selects a linear burst mode, a high selects an interleaved burst sequence. both burst counters use a0 and a1 in the burst sequence, and will wrap-around when incremented suffi- ciently. a high input on adv/ld will increment the internal burst counter regardless of the state of chip enables inputs or we . we is latched at the beginning of a burst cycle. therefore, the type of access (read or write) is maintained throughout the burst sequence. single write accesses write access are initiated when the following conditions are satisfied at clock rise: (1) cen is asserted low, (2) ce 1 , ce 2 , and ce 3 are all asserted active, and (3) the write signal we is asserted low. the address presented to a x is loaded into the address register. the write signals are latched into the control logic block. on the subsequent clock rise the data lines are automatically three-stated regardless of the state of the oe input signal. this allows the external logic to present the data on dq and dqp (dq a,b,c,d /dp a,b,c,d for cy7c1370b and dq a,b /dp a,b for cy7c1372b). in addition, the address for the subsequent access (read/write/deselect) is latched into the address register (provided that the appropriate control signals are asserted). on the next clock rise the data presented to dq and dp (dq a,b,c,d /dp a,b,c,d for cy7c1370b and dq a,b /dp a,b for cy7c1372b) (or a subset for byte write operations, see write cycle description table for details) inputs is latched into the device and the write is complete. the data written during the write operation is controlled by bws (bws a,b,c,d for cy7c1370b and bws a,b for cy7c1372b) signals. the cy7c1370b/cy7c1372b provides byte write capability that is described in the write cycle description table. asserting the write enable input (we ) with the selected byte write select (bws ) input will selectively write to only the desired bytes. bytes not selected during a byte write operation will remain unaltered. a synchronous self-timed write mechanism has been provided to simplify write operations. byte write capability has been included in order to greatly simplify read/modify/write sequences, which can be reduced to simple byte write operations. because the cy7c1370b/cy7c1372b is a common i/o device, data should not be driven into the device while the outputs are active. the oe can be deasserted high before presenting data to the dq and dp (dq a,b,c,d /dp a,b,c,d for cy7c1370b and dq a,b /dp a,b for cy7c1372b) inputs. doing so will three-state the output drivers. as a safety precaution, dq and dp (dq a,b,c,d /dp a,b,c,d for cy7c1370b and dq a,b /dp a,b for cy7c1372b) are automatically three-stated during the data portion of a write cycle, regardless of the state of oe . burst write accesses the cy7c1370b/cy7c1372b has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four write operations without reasserting the address inputs. adv/ld must be driven low in order to load the initial address, as described in the single write access section above. when adv/ld is driven high on the subse- quent clock rise, the chip enables (ce 1 , ce 2 , and ce 3 ) and we inputs are ignored and the burst counter is incremented. the correct bws (bws a,b,c,d for cy7c1370b and bws a,b for cy7c1372b) inputs must be driven in each cycle of the burst write in order to write the correct bytes of data.
cy7c1370b cy7c1372b document #: 38-05197 rev. *c page 8 of 27 cycle description truth table [1, 2, 3, 4, 5, 6] operation address used ce cen adv/ ld/ we bws x clk comments deselected external 1 0 l x x l ? h i/os three-state following next recognized clock. suspend ? x1 x x xl ? h clock ignored, all operations suspended. begin read external 0 0 0 1 x l ? h address latched. begin write external 0 0 0 0 valid l ? h address latched, data presented two valid clocks later. burst read operation internal x 0 1 x x l ? h burst read operation. previous access was a read operation. addresses incremented internally in conjunction with the state of mode. burst write operation internal x 0 1 x valid l ? h burst write operation. previous access was a write operation. addresses incremented internally in conjunction with the state of mode. bytes written are deter- mined by bws [d:a] . interleaved burst sequence first address second address third address fourth address a[1:0] a[1:0] a[1:0] a[1:0] 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst sequence first address second address third address fourth address a[1:0] a[1:0] a[1:0] a[1:0] 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 notes: 1. x = ? don't care, ? 1 = logic high, 0 = logic low, ce stands for all chip enables active. bws x = 0 signifies at least one byte write select is active; bws x = valid signifies that the desired byte write selects are asserted. see write cycle description table for details. 2. write is defined by we and bws x . see write cycle description table for details. 3. the dq and dp pins are controlled by the current cycle and the oe signal. 4. cen = 1 inserts wait states. 5. device will power-up deselected and the i/os in a three-state condition, regardless of oe . 6. oe assumed low.
cy7c1370b cy7c1372b document #: 38-05197 rev. *c page 9 of 27 sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conservation ? sleep ? mode. two clock cycles are required to enter into or exit from this ? sleep ? mode. while in this mode, data integrity is guaranteed. accesses pending when entering the ? sleep ? mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected prior to entering the ? sleep ? mode. ce s, adsp , and adsc must remain inactive for the duration of t zzrec after the zz input returns low. zz mode electrical characteristics parameter description test conditions min. max. unit i ddzz sleep mode standby current zz > v dd ? 0.2v 20 ma t zzs device operation to zz zz > v dd ? 0.2v 2t cyc ns t zzrec zz recovery time zz < 0.2v 2t cyc ns write cycle descriptions [1, 2] function (cy7c1370b) we bws d bws c bws b bws a read 1 x x x x write - no bytes written 0 1 1 1 1 write byte 0 - (dqa and dpa) 01110 write byte 1 - (dqb and dpb) 01101 write bytes 1, 0 01100 write byte 2 - (dqc and dpc) 01011 write bytes 2, 0 01010 write bytes 2, 1 01001 write bytes 2, 1, 0 0 1 0 0 0 write byte 3 - (dqd and dpd) 00111 write bytes 3, 0 00110 write bytes 3, 1 00101 write bytes 3, 1, 0 0 0 1 0 0 write bytes 3, 2 00011 write bytes 3, 2, 0 0 0 0 1 0 write bytes 3, 2, 1 0 0 0 0 1 write all bytes 0 0 0 0 0 function (cy7c1372b) we bws b bws a read 1 x x write - no bytes written 0 1 1 write byte 0 - (dqa and dpa) 0 1 0 write byte 1 - (dqb and dpb) 0 0 1 write both bytes 0 0 0
cy7c1370b cy7c1372b document #: 38-05197 rev. *c page 10 of 27 ieee 1149.1 serial boundary scan (jtag) the cy7c1370b/cy7c1372b incorporates a serial boundary scan test access port (tap) in the bga package only. the tqfp package does not offer this functionality. this port operates in accordance with ieee standard 1149.1 ? 1900, but does not have the set of functions required for full 1149.1 compliance. these functions from the ieee specification are excluded because their inclusion places an added delay in the critical speed path of the sram. note that the tap controller functions in a manner that does not conflict with the operation of other devices using fully 1149.1-compliant taps. the tap operates using jedec standard 3.3v i/o logic levels. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are inter- nally pulled up and may be unconnected. they may alternately be connected to v dd through a pull-up resistor. tdo should be left unconnected. upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. test access port ? test clock the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this pin unconnected if the tap is not used. the pin is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi pin is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instruction register, see the tap controller state diagram. tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most significant bit (msb) on any register. test data-out (tdo) the tdo output pin is used to serially clock data-out from the registers. the output is active depending upon the current state of the tap state machine (see tap controller state diagram). the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and may be performed while the sram is operating. at power-up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo pins and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction registers. data is serially loaded into the tdi pin on the rising edge of tck. data is output on the tdo pin on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo pins as shown in the tap controller block diagram. upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in the captureir state, the two least significant bits are loaded with a binary ? 01 ? pattern to allow for fault isolation of the board level serial test path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain states. the bypass register is a single-bit register that can be placed between tdi and tdo pins. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the i/o pins on the sram. several no connect (nc) pins are also included in the scan register to reserve pins for higher density devices. the 36 configuration has a 70-bit-long register, and the 18 configuration has a 51-bit-long register. the boundary scan register is loaded with the contents of the ram i/o ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo pins when the controller is moved to the shift-dr state. the extest, sample/preload and sample z instructions can be used to capture the contents of the i/o ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has a vendor code and other information described in the identification register definitions table. tap instruction set eight different instructions are possible with the three-bit instruction register. all combinations are listed in the instruction code table. three of these instructions are listed as reserved and should not be used. the other five instruc- tions are described in detail below. the tap controller used in this sram is not fully compliant with the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. the tap controller cannot be used to load address, data, or control signals into the sram and cannot preload the i/o buffers. the
cy7c1370b cy7c1372b document #: 38-05197 rev. *c page 11 of 27 sram does not implement the 1149.1 commands extest or intest or the preload portion of sample/preload; rather it performs a capture of the i/o ring when these instruc- tions are executed. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo pins. to execute the instruction once it is shifted in, the tap controller needs to be moved into the update-ir state. extest extest is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. extest is not implemented in the tap controller, and therefore this device is not compliant with the 1149.1 standard. the tap controller does recognize an all-0 instruction. when an extest instruction is loaded into the instruction register, the sram responds as if a sample/preload instruction has been loaded. there is one difference between the two instructions. unlike the sample/preload instruction, extest places the sram outputs in a high-z state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo pins and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo pins when the tap controller is in a shift-dr state. it also places all sram outputs into a high-z state. sample/preload sample/preload is a 1149.1 mandatory instruction. the preload portion of this instruction is not implemented, so the tap controller is not fully 1149.1-compliant. when the sample/preload instructions are loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. the user must be aware that the tap controller clock can only operate at a frequency up to 10 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output will undergo a transition. the tap may then try to capture a signal while in transition (metastable state). this will not harm the device, but there is no guarantee as to the value that will be captured. repeatable results may not be possible. to guarantee that the boundary scan register will capture the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controller ? s capture set-up plus hold times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/preload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck# captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. note that since the preload part of the command is not implemented, putting the tap into the update to the update-dr state while performing a sample/preload instruction will have the same effect as the pause-dr command. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo pins. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. reserved these instructions are not implemented but are reserved for future use. do not use these instructions.
cy7c1370b cy7c1372b document #: 38-05197 rev. *c page 12 of 27 tap controller state diagram test-logic reset test-logic/ idle select dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select ir-scan capture-dr shift-ir exit1-ir pause-ir exit2-ir update-ir 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 note: 7. the 0/1 next to each state represents the value at tms at the rising edge of tck.
cy7c1370b cy7c1372b document #: 38-05197 rev. *c page 13 of 27 tap controller block diagram 0 0 1 2 . . 29 30 31 boundary scan register identification register 0 1 2 . . . . . 0 1 2 instruction register bypass register selection circuitry selection circuitry tap controller tdi tdo tck tms tap electrical characteristics over the operating range [8, 9] parameter description test conditions min. max. unit v oh1 output high voltage i oh = ? 4.0 ma 2.4 v v oh2 output high voltage i oh = ? 100 a v dd ? 0.2 v v ol1 output low voltage i ol = 8.0 ma 0.4 v v ol2 output low voltage i ol = 100 a 0.2 v v ih input high voltage 1.7 v dd + 0.3 v v il input low voltage ? 0.5 0.7 v i x input load current gnd v i v ddq ? 5 5 a notes: 8. all voltage referenced to ground. 9. overshoot: v ih (ac)< v dd +1.5v for t< t tcyc /2, undershoot: v il (ac)< 0.5v for t< t tcyc /2, power-up: v ih <2.6v and v dd <2.4v and v ddq <1.4v for t<200 ms.
cy7c1370b cy7c1372b document #: 38-05197 rev. *c page 14 of 27 tap ac switching characteristics over the operating range [10, 11] parameter description min. max unit t tcyc tck clock cycle time 100 ns t tf tck clock frequency 10 mhz t th tck clock high 40 ns t tl tck clock low 40 ns set-up times t tmss tms set-up to tck clock rise 10 ns t tdis tdi set-up to tck clock rise 10 ns t cs capture set-up to tck rise 10 ns hold times t tmsh tms hold after tck clock rise 10 ns t tdih tdi hold after clock rise 10 ns t ch capture hold after clock rise 10 ns output times t tdov tck clock low to tdo valid 20 ns t tdox tck clock low to tdo invalid 0 ns notes: 10. t cs and t ch refer to the set-up and hold time requirements of latching data from the boundary scan register. 11. test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns. tap timing and test conditions (a) tdo c l = 20 pf z 0 = 50 ? gnd 1.25v test clock test mode select tck tms test data-in tdi te s t d a ta - o u t tdo t tcyc t tmsh t tl t th t tmss t tdis t tdih t tdov t tdox 50 ? 2.5v 0v all input pulses 1.25v
cy7c1370b cy7c1372b document #: 38-05197 rev. *c page 15 of 27 identification register definitions instruction field 512k 36 1m 18 description revision number (31:28) xxxx xxxx reserved for version number device depth (27:23) 00111 01000 defines depth of sram. 512k or 1m device width (22:18) 00100 00011 defines width of the sram. 36 or 18 cypress device id (17:12) xxxxx xxxxx reserved for future use cypress jedec id (11:1) 00011100100 00011100100 allows unique identification of sram vendor scan register sizes register name bit size ( 18) bit size ( 36) instruction 3 3 bypass 1 1 id 32 32 boundary scan 51 70 identification codes instruction code description extest 000 captures the i/o ring contents. places the boundary scan register between the tdi and tdo. forces all sram outputs to high-z state. this instruction is not 1149.1-compliant. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operation. sample z 010 captures the i/o contents. places the boundary scan register between tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use. this instruction is reserved for future use. sample/preload 100 captures the i/o ring contents. places the boundary scan register between tdi and tdo. does not affect the sram operation. this instruction does not implement 1149.1 preload function and is therefore not 1149.1-compliant. reserved 101 do not use. this instruction is reserved for future use. reserved 110 do not use. this instruction is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operation.
cy7c1370b cy7c1372b document #: 38-05197 rev. *c page 16 of 27 boundary scan order (512k 36) bit # signal name bump id bit # signal name bump id 1 a 2r 36 ce 3 6b 2 a 3t 37 bws a 5l 3 a 4t 38 bws b 5g 4 a 5t 39 bws c 3g 5 a 6r 40 bws d 3l 6 a 3b 41 ce 2 2b 7 a 5b 42 ce 1 4e 8 dpa 6p 43 a 3a 9 dqa 7n 44 a 2a 10 dqa 6m 45 dpc 2d 11 dqa 7l 46 dqc 1e 12 dqa 6k 47 dqc 2f 13 dqa 7p 48 dqc 1g 14 dqa 6n 49 dqc 1d 15 dqa 6l 50 dqc 1d 16 dqa 7k 51 dqc 2e 17 nc 7t 52 dqc 2g 18 dqb 6h 53 dqc 1h 19 dqb 7g 54 sn 5r 20 dqb 6f 55 dqd 2k 21 dqb 7e 56 dqd 1l 22 dqb 6d 57 dqd 2m 23 dqb 7h 58 dqd 1n 24 dqb 6g 59 dqd 2p 25 dqb 6e 60 dqd 1k 26 dpb 7d 61 dqd 2l 27 a 6a 62 dqd 2n 28 a 5a 63 dpd 1p 29 a 4g 64 mode 3r 30 a 4a 65 a 2c 31 adv/ld 4b 66 a 3c 32 oe# 4f 67 a 5c 33 cen# 4m 68 a 6c 34 we# 4h 69 a1 4n 35 clk 4k 70 a0 4p boundary scan order (1m 18) bit # signal name bump id bit # signal name bump id 1 a 2r 36 dqb 2e 2 a 2t 37 dqb 2g 3 a 3t 38 dqb 1h 4 a 5t 39 sn 5r 5 a 6r 40 dqb 2k 6 a 3b 41 dqb 1l 7 a 5b 42 dqb 2m 8 dqa 7p 43 dqb 1n 9 dqa 6n 44 dpb 2p 10 dqa 6l 45 mode 3r 11 dqa 7k 46 a 2c 12 nc 7t 47 a 3c 13 dqa 6h 48 a 5c 14 dqa 7g 49 a 6c 15 dqa 6f 50 a1 4n 16 dqa 7e 51 a0 4p 17 dpa 6d 18 a6t 19 a6a 20 a5a 21 a4g 22 a4a 23 adv/ld 4b 24 oe 4f 25 cen 4m 26 we 4h 27 clk 4k 28 ce 3 6b 29 bws a5l 30 bws b3g 31 ce 2 2b 32 ce 1 4e 33 a3a 34 a2a 35 dqb 1d
cy7c1370b cy7c1372b document #: 38-05197 rev. *c page 17 of 27 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ? 65 c to +150 c ambient temperature with power applied............................................. ? 55 c to +125 c supply voltage on v dd relative to gnd ....... ? 0.5v to +4.6v dc voltage applied to outputs in high z state [13] ................................ ? 0.5v to v ddq + 0.5v dc input voltage [13] ............................ ? 0.5v to v ddq + 0.5v current into outputs (low) ........................................ 20 ma static discharge voltage........................................... >1500v (per mil-std-883, method 3015) latch-up current................................................... >200 ma operating range range ambient temperature [12] v dd [15] v ddq [15] commercial 0 c to +70 c 3.3v 2.5v ? 5% industrial ? 40 c to +85 c ? 5%/+10% 3.3v + 10% electrical characteristics over the operating range [14] parameter description test conditions min. max. unit v dd power supply voltage 3.135 3.63 v v ddq i/o supply voltage 2.375 v dd v v oh output high voltage v dd = min., i oh = ? 1.0 ma v ddq = 2.5v 2.0 v v dd = min., i oh = ? 4.0 ma v ddq = 3.3v 2.4 v v ol output low voltage v dd = min., i ol = 1.0 ma v ddq = 2.5v 0.4 v v dd = min., i ol = 8.0 ma v ddq = 3.3v 0.4 v v ih input high voltage v ddq = 3.3v 2 v dd +0.5 v v ddq = 2.5v 1.7 v dd +0.5 v v il input low voltage v ddq = 3.3v ? 0.3 0.8 v v ddq = 2.5v ? 0.3 0.7 v i x input load current gnd < v i < v ddq 5 a input current of mode ? 30 30 a input current of zz input = v ss ? 30 30 a i oz output leakage current gnd < v i < v ddq, output disabled 5 a i dd v dd operating supply v dd = max., i out = 0 ma, f = f max = 1/t cyc 5.0-ns cycle, 200 mhz 315 ma 6.0-ns cycle, 167 mhz 285 ma 6.7-ns cycle, 150 mhz 265 ma 7.5-ns cycle, 133 mhz 245 ma i sb1 automatic ce power-down current ? ttl inputs max. v dd , device deselected, v in > v ih or v in < v il f = f max = 1/t cyc 5.0-ns cycle, 200 mhz 140 ma 6.0-ns cycle, 167 mhz 120 ma 6.7-ns cycle, 150 mhz 110 ma 7.5-ns cycle, 133 mhz 105 ma i sb2 automatic ce power-down current ? cmos inputs max. v dd , device deselected, v in < 0.3v or v in > v ddq ? 0.3v, f = 0 all speed grades 20 ma i sb3 automatic ce power-down current ? cmos inputs max. v dd , device deselected, v in < 0.3v or v in > v ddq ? 0.3v, f = 0 6.0-ns cycle, 200 mhz 110 ma 6.0-ns cycle, 167 mhz 100 ma 6.7-ns cycle, 150 mhz 90 ma 7.5-ns cycle, 133 mhz 85 ma i sb4 automatic cs power-down current ? ttl inputs max. v dd , device deselected, v in > v ih or v in < v il , f = 0 all speeds 50 ma notes: 12. t a is the case temperature. 13. minimum voltage equals -2.0v for pulse durations of less than 20 ns. 14. the load used for v oh and v ol testing is shown in figure (b) of the a/c test conditions. 15. power supply ramp up should be monotonic.
cy7c1370b cy7c1372b document #: 38-05197 rev. *c page 18 of 27 capacitance [17] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v dd = v ddq = 3.3v 3 pf c clk clock input capacitance 3 pf c i/o i/o capacitance 3 pf ac test loads and waveforms output r = 317 ? r = 351 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v l = 1.5v v ddq all input pulses [16] v cc gnd 90% 10% 90% 10% < 1v/ns < 1v/ns (c) thermal resistance [17] description test conditions q ja (junction to ambient) q jc (junction to case) unit 119 bga still air, soldered on a 114.3 101.6 1.57 mm3, 2-layer board 41.54 6.33 c/w 165 fbga 44.51 2.38 c/w 100-pin tqfp still air, soldered on a 4.25 1.125 inch, 4-layer printed circuit board 25 9 c/w notes: 16. input waveform should have a slew rate of > 1 v/ns. 17. tested initially and after any design or process change that may affect these parameters.
cy7c1370b cy7c1372b document #: 38-05197 rev. *c page 19 of 27 switching characteristics over the operating range [18] parameter description -200 -166 -150 -133 unit min. max. min. max. min. max. min. max. clock t cyc clock cycle time 5 6.0 6.7 7.5 ns t ch clock high 1.8 2.1 2.3 2.5 ns t cl clock low 1.8 2.1 2.3 2.5 ns output times t co data output valid after clk rise 3.0 3.4 3.8 4.2 ns t eov oe low to output valid [17, 19, 21] 3.0 3.4 3.8 4.2 ns t doh data output hold after clk rise 1.3 1.3 1.3 1.3 ns t chz clock to high-z [17, 18, 19, 20, 21] 3.0 3.0 3.0 3.5 ns t clz clock to low-z [17, 18, 19, 20, 21] 1.3 1.3 1.3 1.3 ns t eohz oe high to output high-z [18, 19, 21] 4.0 4.0 4.0 4.0 ns t eolz oe low to output low-z [18, 19, 21] 00 0 0 ns set-up times t as address set-up before clk rise 1.4 1.5 1.5 1.5 ns t ds data input set-up before clk rise 1.4 1.5 1.5 1.5 ns t cens cen set-up before clk rise 1.4 1.5 1.5 1.5 ns t wes we , bws x set-up before clk rise 1.4 1.5 1.5 1.5 ns t als adv/ld set-up before clk rise 1.4 1.5 1.5 1.5 ns t ces chip select set-up 1.4 1.5 1.5 1.5 ns hold times t ah address hold after clk rise 0.4 0.5 0.5 0.5 ns t dh data input hold after clk rise 0.4 0.5 0.5 0.5 ns t cenh cen hold after clk rise 0.4 0.5 0.5 0.5 ns t weh we , bw x hold after clk rise 0.4 0.5 0.5 0.5 ns t alh adv/ld hold after clk rise 0.4 0.5 0.5 0.5 ns t ceh chip select hold after clk rise 0.4 0.5 0.5 0.5 ns notes: 18. unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.5v, in put pulse levels of 0 to 3.0v, and output loading of the specified i ol /i oh and load capacitance. shown in (a), (b), and (c) of ac test loads. 19. t chz , t clz , t oev , t eolz , and t eohz are specified with ac test conditions shown in part (a) of ac test loads. transition is measured 200 mv from steady-state voltage. 20. at any given voltage and temperature, t eohz is less than t eolz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst-case user conditions. device is designed to achieve high-z prior to low-z under the same system conditions. 21. this parameter is sampled and not 100% tested.
cy7c1370b cy7c1372b document #: 38-05197 rev. *c page 20 of 27 switching waveforms cen clk address ce we and data in/out t cyc t ch t cl ra1 t ah t as t ws t wh t ces t ceh t co q4 q1 = don ? t care = undefined the combination of we and bws x (x = a, b, c, d for cy7c1370b and x = a, b for cy7c1372b) define a write cycle out d2 in d5 in out read write deselect write read read read suspend read deselect deselect wa2 ra3 ra4 wa5 ra6 ra7 t clz t doh q3 out t chz device originally deselected q7 out t chz t cens t cenh t doh bws x read/write/deselect sequence cen high blocks q6 out all synchronous inputs t ds t dh (see write cycle description table). ce is the combination of ce 1 , ce 2 , and ce 3 . all chip enables need to be active in order to select the device. any chip enable can deselect the device. rax stands for read address x, wax write address x, dx stands for data-in for location x, qx stands for data-out for location x. adv/ld held low. oe held low.
cy7c1370b cy7c1372b document #: 38-05197 rev. *c page 21 of 27 switching waveforms (continued) adv/ld clk address ce data in/out t cyc t ch t cl t als t alh ra1 t ah t as t ces t ceh t co q1 = don ? t care = undefined the combination of we and bws x (x = a, b c, d) define a write cycle (see write cycle description table). out begin read burst read t clz t doh ce is the combination of ce 1 , ce 2 , and ce 3 . all chip enables need to be active in order to select the device. any chip enable can deselect the device. rax stands for read address x, wa stands for device originally deselected write address x, dx stands for data-in for location x, qx stands for data-out for location x. cen held wa2 q1+1 out q1+2 out q1+3 out ra3 t clz t chz d2+1 in d2+2 in d2+3 in d2 in t co q3 out t ds t dh burst read burst read begin write burst write burst write burst write begin read burst read burst read burst sequences bws x t ws t wh we t ws t wh low. during burst writes, byte writes can be conducted by asserting the appropriate bws x input signals. burst order determined by the state of the mode input. cen held low. oe held low.
cy7c1370b cy7c1372b document #: 38-05197 rev. *c page 22 of 27 note: 22. device must be deselected when entering zz mode. see cycle descriptions table for all possible signal conditions to deselect the device. 23. i/os are in three-state when exiting zz sleep mode. switching waveforms (continued) oe three-state i/os oe timing t eohz t eov t eolz clk ce 1 ce 3 low high zz t zzs t zzrec i dd i dd (active) three-state i/os zz mode timing [22, 23] ce 2 i ddzz
cy7c1370b cy7c1372b document #: 38-05197 rev. *c page 23 of 27 ordering information speed (mhz) ordering code package name package type operating range 200 cy7c1370b-200ac cy7c1372b-200ac a101 100-lead thin quad flat pack commercial cy7c1370b-200bgc cy7c1372b-200bgc bg119 119 pbga CY7C1370B-200BZC cy7c1372b-200bzc ba165a 165 fbga 167 cy7c1370b-167ac cy7c1372b-167ac a101 100-lead thin quad flat pack cy7c1370b-167bgc cy7c1372b-167bgc bg119 119 pbga cy7c1370b-167bzc cy7c1372b-167bzc ba165a 165 fbga 150 cy7c1370b-150ac cy7c1372b-150ac a101 100-lead thin quad flat pack cy7c1370b-150bgc cy7c1372b-150bgc bg119 119 pbga cy7c1370b-150bzc cy7c1372b-150bzc ba165a 165 fbga 133 cy7c1370b-133ac cy7c1372b-133ac a101 100-lead thin quad flat pack cy7c1370b-133bgc cy7c1372b-133bgc bg119 119 pbga cy7c1370b-133bzc cy7c1372b-133bzc ba165a 165 fbga 167 cy7c1370b-167ai cy7c1372b-167ai a101 100-lead thin quad flat pack industrial cy7c1370b-167bgi cy7c1372b-167bgi bg119 119 bga cy7c1370b-167bzi cy7c1372b-167bzi ba165a 165 fbga 150 cy7c1370b-150ai cy7c1372b-150ai a101 100-lead thin quad flat pack cy7c1370b-150bgi cy7c1372b-150bgi bg119 119 bga cy7c1370b-150bzi cy7c1372b-150bzi ba165a 165 fbga 133 cy7c1370b-133ai cy7c1372b-133ai a101 100-lead thin quad flat pack cy7c1370b-133bgi cy7c1372b-133bgi bg119 119 pbga cy7c1370b-133bzi cy7c1372b-133bzi ba165a 165 fbga shaded areas contain advance information.
cy7c1370b cy7c1372b document #: 38-05197 rev. *c page 24 of 27 package diagrams 100-pin thin plastic quad flatpack (14 x 20 x 1.4 mm) a101 51-85050-a
cy7c1370b cy7c1372b document #: 38-05197 rev. *c page 25 of 27 package diagrams (continued) 165-ball fbga (13 x 15 x 1.2 mm) bb165a 51-85122-*c
cy7c1370b cy7c1372b document #: 38-05197 rev. *c page 26 of 27 ? cypress semiconductor corporation, 2002. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. nobl and zero bus latency are trademarks of cypress semiconductor corporation. all product and company names mentioned in this document may be the trademarks of their respective holders. package diagrams (continued) 51-85115-*b 119-lead pbga (14 x 22 x 2.4 mm) bg119
cy7c1370b cy7c1372b document #: 38-05197 rev. *c page 27 of 27 document history page document title: cy7c1370b/cy7c1372b 512k x 36/1m x 18 pipelined sram with nobl ? architecture document number: 38-05197 rev. ecn no. issue date orig. of change description of change ** 112033 12/09/01 dsg change from spec number: 38-01070 to 38-05197 *a 116852 08/19/02 cjm changed v ddq - max = 3.63 to v dd added v ih - max = v dd +0.5 changed t doh from 1.5 to 1.3 ns *b 121531 11/19/02 dsg updated package diagrams 51-85115 (bg119) to rev. *b and 51-85122 (bb165a) to rev. *c *c 123127 01/18/03 rbi add power up requirments to operating range information

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